Frequently, design planning (e.g., die size/device selection, layout analysis, power estimation, etc.) is performed early in a design cycle. Because the design planning can be performed a long time before the actual design is complete (i.e., RTL finished), design planning tasks are often performed with “rules of thumb” based on experience of the designer. When the design planning tasks are not performed early or the design planning tasks are not estimated correctly, a project can suffer a major set-back. For example, a project can be set-back when design analysis assumptions (i.e., ability to fit a design into a particular programmable platform device) are incorrect.
Complex designs that are suitable candidates for use with platform (or structured) application specific integrated circuits (platform ASICS) can be incomplete when a customer needs to make design decisions (e.g., select the platform, device or slice), calculate cost and margin based on the slice selected, etc.). Serious problems can arise when, later in the design process, the customer finds that the design does not fit the selected platform, device or slice. Often, parts of the design can be complete (i.e., third party IP and legacy code) and parts of the design can still be in development (i.e., new design blocks).
As used herein, the term slice generally refers to a partially manufactured semiconductor device in which the wafer layers up to the connectivity layers have been fabricated. The slice generally comprises a base semiconductor wafer (e.g., from silicon, silicon-on-insulator, silicon germanium, gallium arsenide, other Type II, III, IV, and V semiconductors, etc.). The slice generally comprises a piece of semiconductor material into which blocks or hardmacs have been diffused into the semiconductor layers. Diffusing a semiconductor wafer to create a hardmac simply means that during fabrication of the wafer layers, transistors or other electronic devices have been particularly arranged in the wafer layers to achieve specific functions, such as diffused memory, data transceiver hardware (e.g., I/O PHYs), clock factories (e.g., PLLs, etc.), control I/Os, configurable input/output (I/O) hardmacs, etc. Each of the hardmacs generally has an optimum arrangement and density of transistors to realize a particular function. The slice may further comprise an area of transistor fabric for further development of the slice using a suite of generation tools described herein. The transistor fabric generally comprises an array of prediffused transistors in a regular pattern that can be logically configured by placement of one or more metal layers. Different slices may contain different amounts and arrangements of transistor fabric, different amounts of diffused and/or compiled memories, both fixed and configurable I/O blocks, clocks, etc. depending upon the purpose of the final integrated chip.
Accurately estimating the requirements of a design can be difficult for customers, especially less experienced ones. Currently there are two ways design requirements can be estimated: 1) the engineer estimates the overall gate count (and thus the die area/slice required) based upon experience and design knowledge or 2) the customer works with a manufacturer's field support representative to select a platform, device or slice. In an example of the first method, the engineer may estimate the design will be two million gates, and therefore selects a slice that the datasheet indicates can fit two million gates. With the second method, a more accurate estimation can be made, but the estimation is still subject to accuracy problems.
The first solution is undesirable because of the reliance on the expertise of the engineer. The engineer can easily mis-estimate the overall die size/slice required. Even a manufacturer's field support representative can have limited ability and experience in accurately estimating gate counts due to a lack of available tools. There is currently no cohesive way to collate and interpret all information about a design until the design is completed. A customer may have a datasheet of the existing IP characteristics (i.e., gate count, power usage, etc.) and estimations of the characteristics for any missing blocks. Maintaining, understanding and making decisions based upon the information can be difficult when spread across many different sources.
With conventional tools, users cannot progress with a ‘trial design flow’ until they have all the RTL and memory instantiations. Thus, design planning and/or synthesis cannot be performed to find any large problems early in the design cycle. Furthermore, timing estimation of levels of logic for a given block is not possible until after the RTL is written. Power and utilization estimation (e.g., based on logic density, not just gate count) is also not possible before the RTL is complete. A trial design flow is used on platform ASICs because platform ASICs can have a relatively high routing-related density impact compared with cell-based ASICs where logic has more routing layers.
The ability to accurately predict utilization, power and/or performance before the actual RTL is complete may provide designers with a huge advantage over conventional solutions.